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revision history 512m as4c32m16ms-7bcn/AS4C32M16MS-6BIN - 54 ball fbga package 512m as4c16m32ms-7bcn/as4c16m32ms-6bin - 90 ball fbga package revision details date rev 1.0 preliminary datasheet jun 2016 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice 512m low power mobile sdram (msdr) as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 1/48 - rev.1.0 june 2016
features - 4 banks x 8mbit x 16 organization - 4 banks x 4mbit x 32 organization - high speed data transfer rates up to 166 mhz - full synchronous dynamic ram, with all signals referenced to clock rising edge - single pulsed ras interface - data mask for read/write control - four banks controlled by ba0 & ba1 - programmable cas latency: 2, 3 - programmable wrap sequence: sequential or interleave - programmable burst length: 1, 2, 4, 8, full page for sequential type 1, 2, 4, 8 for interleave type - multiple burst read with single write operation - automatic and controlled precharge command - random column address every clk (1-n rule) - power down mode and clock suspend mode - auto refresh and self refresh - refresh interval: 8192 cycles/64 ms - available in 54-ball (32m x 16) and 90-ball (16m x32)fbga - vdd=1.8v, vddq=1.8v - lvttl interface - drive strength (ds) option: full, 1/2, 1/4 and 3/4 - auto temperature compensated self refresh (auto tcsr) - partial array self refresh (pasr) option: full, 1/ 2, 1/4, 1/8 and 1/16 - deep power down (dpd) mode - programmable power reduction feature by patial array activation during self-refresh - operating temperature range commercial (-25 c to 85 c) industrial (-40 c to +85 c) table 2 . ordering information table 1. key specifications as4c 32 m16m s/as4c16m32ms -6 /7 tck(3) clock cycle time(min.) 6/7.5 ns tac(3) access time from clk (max.) 5/5.4 ns tras row active time(min.) 42/45 ns trc row cycle time(min.) 60/6 7.5 ns part number org temperature maxclock (mhz) package as4c32m 16 m s-7bc n 32 mx16 com m ercial -25c to + 8 5c 133 5 4 - ball fbga as4c32m 16 ms- 6 b i n 32 mx16 industrial - 40 c to +85c 166 5 4 -ball fbga as4c 16 m32m s - 7 b cn 16 mx32 commercial - 25 c to + 8 5c 133 90 - ball fbga as4c16m 32ms- 6 b in 16 mx32 industrial - 40 c to +85c 166 90 - ball fbga as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 2/48 - rev.1.0 june 2016
54 pin (x16) bga pin configuration top view 51 6 8 7 9 f e d c b j h g a 23489: b wtt er 26 wttr weer er 1 wee c er 25 er 24 weer wttr er 3 er 2 d er 23 er 22 wttr weer er 4 er 4 e er 21 er : weer wttr er 7 er 6 fer9 eov 2 wtt wee mer n er 8 g vern dl dlf dbt sbt x f h b23 b22 b: cb1 cb2 dt i b 9 b 8 b 7 b 1 b 2 b 210b q k wtt b6 b5 b4 b3 wee opuf!2;!uif!eov!qj o!n vtu!cf!dpoofdufe!up!w t t -!w t t r -!ps!m f gu!gm pbujoh/ 65c bm m !)7y :*!d t q 512mb mobile sdram addressing configuration 32mx16 16mx32 16mx32 (reduced page size) # of bank 4 4 4 bank address ba0 ~ ba1 ba0 ~ ba1 ba0 ~ ba1 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a12 a0 ~ a12 a0 ~ a13 column address a0 ~ a9 a0 ~ a8 a0 ~ a7 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 3/48 - rev.1.0 june 2016
90 pin (x32) bga pin configuration top view 5 6 8 97 f e d c b j h g a k / 0 1 3 5 23489: b er37 er35 wtt wee er34 er32 c er39 weer wttr weer wttr er2: d wttr er38 er36 er33 er31 weer e wttr er3: er41 er28 er29 weer f weer er42 od od er27 wttr g wtt er n 4 b4 b3 er n 3 wee h b5b6b7b210bqb1b2 ib8b9b23 b24 2 cb2 b22 k dl dlf b: cb1 dt sbt lern2 eov 3 od dbt x f ern1 m weer er9 wtt wee er8 wttr n wttr er21 er: er7 er6 weer o wttr er23 er25 er2 er4 weer q er22 weer wttr weer wttr er5 s er24 er26 wtt wee er1 er3 o p uf !2 ;!b 2 4 !j t!pom z!bwbj m bcmf!gps!sfevdfe!qbhf.tj {f!dpogjhvsbuj po/ o p uf !3 ;!u i f !e o v !q j o!n vtu!cf!dpoofdufe!up!wtt-!wttr -!ps!m f gu!gm pbuj oh/ :1c bm m !)7y 26*!d t q as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 4/48 - rev.1.0 june 2016
description the as4c32m16ms / as4c16m32ms is a four bank synchron ous dram organized as 4 banks x 8mbit x 16 and 4 banks x 4mbit x 32. the as4c32m16ms / as4c16m32ms achieves high speed data transfer rates up to 166 mhz by em ploying a chip architecture that prefetches multiple bits and then sync hronizes the output data to a system cloc k. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleaved fa shion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 166 mhz is possible depending on burst length, cas latency and speed grade of the device. signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a13 input level ? during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) and a0-a13 defines the row address (ra0-ra13) for 16mx32 reduced page size when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9) for 32mx16, a0-a8 defines the column address (ca0-ca8) for 16mx32 and a0-a7 de- fines tthe column address (ca0-ca7) for 16mx32 reduced page size when sampled at the rising clock edge. in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will ba0 and ba1 are used to define which bank to precharge. ba0, ba1 input level ? selects which bank is to be active. dqx input output level ? data input/output pins operate in the same manner as on conventional drams. ldqm udqm (dm0~3) input pulse active high the data input/output mask plac es the dq buffers in a high impedance state when sam- pled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be wri tten if it is low but blocks the write operation if dqm is high. if it?s high, ldm corres ponds to dq0-dq7, and udm corresponds to data on dq8-dq15 in 32mx16. dm0 corresponds to dq0-dq7, dm1 corresponds to data on dq8-dq15, dm2 corresponds to dq16-dq23, and dm3 corresponds to data on dq24- dq31 in 16mx32. vdd, vss supply power and ground for the input buffers and the core logic. vddq vssq supply ? ? isolated power supply and ground for t he output buffers to provide improved noise immunity. nc input ? ? no connect. as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 5/48 - rev.1.0 june 2016
operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. th e following list shows the thruth table for the operation commands. notes: 1. v = valid , x = don?t care, l = low level, h = high level 2. cken signal is input level when commands are provided, ck en-1 signal is input level one clock before the commands are provided. 3. these are state of bank designated by ba0, ba1 signals. 4. power down mode can not entry in the burst cycle. 5. after deep power down mode exit a full new initialization of memory device is mandatory 6. extended grade does not guarantee self-refresh function operation device state cke n-1 cke ncs ras cas we dqm a0-9, a11,12 a10 ba0 ba1 row activate idle 3 hxllhhxvv v read active 3 hxlhlhxvl v read w/autoprecharge active 3 hxlhlhxvh v write active 3 hxlhllxvl v write with autoprecharge active 3 hxlhllxvh v row precharge any h x l l h l x x l v precharge all any h x l l h l x x h x mode register set idle h x l l l l x v v v no operation any h x l h h h x x x x device deselect any h x h x x x x x x x auto refresh idle h h l l l h x x x x self refresh entry 6 idle hllllhxxxx self refresh exit 6 idle (self refr.) l h hxxx xxx x lhhx power down entry idle active 4 hl hxxx xxx x lhhx power down exit any (power down) lh hxxx xxx x lhhl data write/output enable active h x x x x x l x x x data write/output disable active h x x x x x h x x x deep power down entry idle h l l h h l x x x x deep power down exit deep power- down lhxxxxxxx x as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 6/48 - rev.1.0 june 2016
power on and initialization the defa ult power on state of the mode register is supplier specific a nd may be un defined. the following power on and initializ ation sequence guarantees the device is preconditioned to ea ch users specific needs. like a c onventional dram, the syn chronous dram must be po wered up and initialized in a pre -defin ed manner. during power on, all vdd and vddq pins must be built up simultaneously to the specified voltag e when the input signals are held in the ?nop? sta te. the clk signal mus t be started at the same time. after power on, the device requires a 100s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100us period and continuing at least through the end of this period, command inhibit or nop commands should be applied. after the 100us delay is satisfied by issuing at least one command inhibit or nop command, a precharge command must be issued. all banks must then be pre-charged, which places the device in the all banks idle state. once all banks have been pre-charged, the mode register and extended mode register set command must be is sued to initialize the mode register. a minimum of two auto refresh cy cles (cbr) are also required. these may be done before or after programming the mode register. failure to follow these steps may lead to unpredic table start-up modes. programming the mode register the mode register desi gnates the operation mode at the read or write cycl e. this register is di vided into 4 fields. a burst length field to set the length of the burst, an addres sing selection bit to program the column access sequence in a burst cy cle (interleaved or sequential), a cas latency field to set the access time at clock cy cle and a opera tion mode field to differentiate between normal op eration (burst read and burst write) and a s pecial burst read and single write mode. the mode set operation must be done before any activate com- mand after the initial power up. any content of the mode register can be altered by re-executing the mode set c ommand. all banks must be in pre- charged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is re quired. low signals of ras , cas , and we at the positive edge of the clock activate the mode set op eration. address input data at this timing defines pa rameters to be set as shown in the previous table. extended mode register the extended mode register controls func tions beyond those controlled by the mode register. these additional functions are unique to the mobile sdram and includes the selection of drive strength (ds). the device has four drive strength options: full, 12, 1/4 or 3/4. and a partial-array self-refresh field (pasr). the pasr fi eld is used to specify whether partial bank 1/2, 1/4, 1/8, 1/16 or all banks of the sdram array are enabled. disabled banks will not be refreshed in self -refresh mode and writ ten data will be lost. when only bank 0 is selected, it?s possible to partially select only half or mo re quarter of bank 0. the default setting for ds is full- strength, while pasr is full memory. both ds and pasr can be set during the initialization sequence and can be modified when the part is idle. add ition ally, the device has internal temperature sensor control self refresh cycle automatically. this is the device internal temperature compensated self re fresh (tcsr). read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the select ed bank is activated and all of sense amplifiers as sociated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a c lock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 166 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8. column addresses are seg mented by the burst length and serial data accesses are done within this boundary. the first column ad dress to be accessed is supplied at the cas timing and the subsequent addresses are generated auto matically by the programmed burst length and its s equence. for example, in a burst length of 8 with interleave sequence, if the first address is ?2?, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 7/48 - rev.1.0 june 2016
address input for mode set (mode register operation) similar to the page mode of conventional dram?s , burst read or write accesses on any col umn addres s are possible once the ras cy cle latches the sense amplifiers. the max imum t ras or the refresh interval time limits the number of random column acc esses. a new bu rst access can be done even before the previous burst ends . the interrupt operation at every clock c ycles is supported. when the previous burst is interrupted, the remaining ad dress es are overridden by the new address with the full burst length. an interrupt which accompanies with an operation change from a read to a write is pos sible by ex ploiting dqm to avoid bus contention. when two or more banks are activated s equentially, interleaved bank read or write operations are possible. with the programmed burs t length, alternate access and pre-charge operations on two or more banks can realize fast s erial data acc ess modes among many different pages. once two or more banks are activated, column to column interleave operation can be done between different pages. an~ a3a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register cas latency a6 a5 a4 latency 0 0 0 reserve 0 0 1 reserve 010 2 011 3 1 0 0 reserve 1 0 1 reserve 1 1 0 reserve 1 1 1 reserve burst length a2 a1 a0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page reserve burst type a3 type 0 sequential 1 interleave operation mode ba1 ba0 an~a10 a9 a8 a7 mode 00 0 000 burst read/burst write 00 0 100 burst read/single write operation mode ba0ba1 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 8/48 - rev.1.0 june 2016
an~ a3a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) tcsr** pasr mode register a6 a5 drive strength 00 full 01 1/2 10 1/4 11 3/4 all have to be set to "0" ba0ba1 partial-array self refresh: a2 a1 a0 banks to be self-refreshed 0 0 0 all banks 0 0 1 1/2 array (ba1=0) 0 1 0 1/4 array (ba1=0, ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 1/8 array (ba1=ba0=0, ra11=0) 1 1 0 1/16 array (ba1=ba0=0, ra11=ra10=0) 1 1 1 reserved 1*) 0*) *)ba1 and ba0 must be 1, 0 to select the extended mode register (vs. the mode register) the extended mode register can be set during the initia lization sequence. once the device is operational, the extended mode register set can be issued anytime when the part is idle. ds drive strength extended grade does not guarantee self-refresh function. * *on-die temperature sensor is used in place of tcsr. setting these bits will have no effect. extended mode register table as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 9/48 - rev.1.0 june 2016
burst length and sequence: refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refr esh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any re- fresh mode. an on-chip address counter increments the word and the bank addresses and no bank infor- mation is required for both refresh mode s. t he chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum t rc time is re- quired between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automa tic refresh operation. the chip has an on-chip timer and the self re- fresh mode is available. it enters the mode when ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high en- ables the clock and initiates the refresh exit opera- tion. after the exit command, at least one t rc delay is required prior to any access command. extended grade does not guarantee self-refresh function. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high? at a clock timing, data outputs are disabled and become high impedance after delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (t rp ) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver cir- cuits except clk and cke are gated off. the power down mode does not perform any refresh opera- tions, therefore the device can?t remain in power down mode longer than the refresh period (t ref ) of the device. exit from this mode is performed by tak- ing cke ?high?. one clock delay is required for mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock before the last data out for cas latencies 2, and two clocks for cas la- tencies 3. if ca10 is high when a write command is a data mask function for writes. when dqm is burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x 0 0 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 f ull page nnn cn, cn+1, cn+2 not supported as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 10/48 - rev.1.0 june 2016
issued, the write with auto-precharge function is initiated. the sdram automatically enters the pre- charge operation a time delay equal to t wr (write recovery time) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2, two clocks before the last data out for cas latency = 3. writes require a time delay twr from the last data out to apply the precharge command. bank selection by address bits: burst termination a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1 x x all banks recommended operation and characteristics t a = -25 to 85 c(commercial); -40 to 125 c(extended) v ss = 0 v; v dd = 1.8 v,v ddq = 1.8v note: 1. all voltages are referenced to v ss . 2. v ih may overshoot to v cc + 2 v for pulse width of < 3ns with 1.8v. v il may undershoot to -2 v for pulse width < 3ns with 1.8v. pulse width measured at 50% points with am plitude measured peak to dc reference. parameter symbol limit values unit notes min. max. supply voltage v dd 1.7 1.95 v i/o supply voltage v ddq 1.7 1.95 v 1, 2 input high voltage (ac) v ih 0.8xv ddq v dd +0.3 v 1, 2 input low voltage (ac) v il ? 0.3 0.3 v 1, 2 output high voltage (i out = ? 0.1 ma) v oh 0.9*v ccq ?v output low voltage (i out = 0.1 ma) v ol ?0 . 2v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 1 1 a output leakage current (dq is disabled, 0 v < v out < v cc ) i o(l) ? 1.5 1.5 a once a burs t read or write operation has been ini- tiated, there are sev eral methods in which to termi- nate the burst operation prematurely. these methods include using another read or write com- mand to interrupt an ex isting burst operation, use a pre- charge command to interrupt a burst cycle and close the active bank , or using the burst stop com- mand to terminate the exis ting burst operation but leave the bank open for future read or write com- mands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid i/o conten- tion. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burs t write operation, then any residual data from the burst writ e cycle will be ignored. data that is presented on the i/o pins before the burst stop command is regis ter ed will be written to the memory. deep power down mode the deep power down mode is an unique with very low standby currents. all internal voltage generators inside the mobile sdram are stopped; all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 11/48 - rev.1.0 june 2016
absolute maximum ratings* operating temperature range (commercial)-25 to 85 c operating temperature range (industrial) -40 to 85 c storage temperature range ............... -55 to 150 c input/output voltage ............................. -0.5 to 2.4 v power supply voltage .......................... -0.5 to 2.4 v *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affe ct device reliability. operating currents t a =-25 to 85 c(commercial)/-40 to 85 c(industrial); v ss = 0 v; v dd = 1.8 v,v ddq = 1.8v(recommended operating conditions unless otherwise noted) notes: 7. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 8. these parameter depend on output loading. specified values are obtained with output open. symbol parameter & test condition max. unit note -6 -7 icc1 operating current t rc = t rcmin. , t rc = t ckmin . active-precharge command cycling, without burst operation 1 bank operation 50 45 ma 7 icc2p precharge standby current in power down mode cs =v ih , cke v il(max) t ck = min. 0.3 0.3 ma 7 icc2n precharge standby current in non-power down mode cs =v ih , cke v il(max) t ck = min. 10 10 ma icc3n no operating current t ck = min, cs = v ih(min) bank ; active state ( 4 banks) cke v ih(min.) 20 20 ma icc3p cke v il(max.) (power down mode) 55m a icc4 burst operating current t ck = min read/write command cycling 75 70 ma 7,8 icc5 auto refresh current t ck = min auto refresh command cycling 95 95 ma 7 izz deep power down current 10 10 ua as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 12/48 - rev.1.0 june 2016
temperature compensated/partial array self-refresh currents parameter & test condition extended mode register a[2:0] tcase [ o c] symb. max. unit note self refresh current self refresh mode cke=low, tck=min, full array activations, all banks 85 o c max. icc6 600 ua 45 o c max. icc6 300 ua self refresh current self refresh mode cke=low, tck=min, 1/2 array activations 85 o c max. icc6 480 ua 45 o c max. icc6 260 ua self refresh current self refresh mode cke=low, tck=min, 1/4 array activation 85 o c max. icc6 420 ua 45 o c max. icc6 250 ua self refresh current self refresh mode cke=low, tck=min, 1/8 array activation 85 o c max. icc6 420 ua 45 o c max. icc6 250 ua self refresh current self refresh mode cke=low, tck=min, 1/16 array activation 85 o c max. icc6 400 ua 45 o c max. icc6 250 ua as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 13/48 - rev.1.0 june 2016
ac characteristics t a = -25 to 85 c(commercial)/-40 to 85 c(industrial) v ss = 0 v; v dd = 1.8 v,v ddq = 1.8v, t t =1 ns # symbol parameter limit values unit note -6 -7 min. max. min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 6 9 ? ? 7.5 9 ? ? ns ns 6 2f ck clock frequency cas latency = 3 cas latency = 2 ? ? 166 110 ? ? 133 110 mhz mhz 3t ac access time from clock cas latency = 3 cas latency = 2 ? _ 5 8 ? _ 5.4 8 ns ns 4t ch clock high pulse width 2.5 ? 2.5 ? ns 5t cl clock low pulse width 2.5 ? 2.5 ? ns 6t t transition tim 0.3 1.2 0.3 1.2 ns 9 setup and hold times 7t ckh cke hold time 1?1?ns 8t cks cke setup time 1.5 ? 1.5 ? ns 9t dh data-in hold time 1?1?ns 10 t ds data-in setup time 1.5 ? 1.5 ? ns 11 t ah address hold time 1?1?ns 12 t as address setup time 1.5 ? 1.5 ? ns 13 t cmh /cs, /ras, /cas, /we, dqm hold time 1.5 1.5 ? ns 14 t cms /cs, /ras, /cas, /we, dqm setup time 0.5 ? 0.5 ? ns 15 t mrd mode register set to command delay 2?2?clk common parameters 16 t rcd row to column delay time 18 ? 19.2 ? ns 17 t rp row precharge time 18 ? 19.2 ? ns 18 t ras row active time 42 100k 45 100k ns 19 t rc active to active/auto refresh command period 60 ? 67.5 ? ns 20 t rrd activate(a) to activate(b) command period 2?2?clk 21 t bdl last data-in to burst stop command1?1?clk12 22 t ccd cas (a) to cas (b) command period 1?1?clk12 23 t cdl last data-in to new read/write com- mand 1?1?clk13 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 14/48 - rev.1.0 june 2016
24 t cked cke to clock disable or power-down entry mode 1?1?clk13 25 t ped cke to clock enable or power-down exit mode 1?1?clk13 refresh cycle 26 t ref refresh period (8192 cycles) ? 64 ? 64 ms 8 27 t xsr exit self refresh to first valid command 112 ? 112.5 ? ns 11 28 t rfc row refresh cycle time 97.5 ? 97.5 ? ns read cycle 29 t oh data out hold time(load) 2.5 ? 2.5 ? ns 30 t ohn data out hold time(no load) 1.8 ? 1.8 ? ns 31 t lz data out to low impedance time 1?1?ns7 32 t hz data out to high impedance time cas latency = 3 cas latency = 2 ? _ 5 8 ? _ 5.4 8 ns ns 33 t roh data-out high-z from precharge command cas latency = 3 cas latency = 2 3 2 ? _ 3 2 ? _ clk clk 12 write cycle 34 t wr write recovery time 15 ? 15 ? ns 10 35 t dal data-in to active command 5?5?clk14,16 36 t dpl data-in to precharge command 2?2?clk15,16 37 t dqd dqm to input data delay 0?0?clk12 38 t dqm dqm to data mask during writes 0?0?clk12 39 t dqz dqm to data high-z during reads 2?2?clk12 40 t dwd write command to input data delay 0?0?clk12 41 t rdl last data-in to precharge command2?2?clk15,16 # symbol parameter limit values unit note -6 -7 min. max. min. max. ac characteristics (cont?d) as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 15/48 - rev.1.0 june 2016
note: 1. a full initialization sequence is required before proper device o peration is ensured. 2. the minimum specifications are used only to indi cate cycle time at whic h proper operat ion over the full temperature range (0 o c< ta <+70 o c standard temperature and -40 o c < ta <+85 o c industrial temperature) is ensured. 3. in addition to meeting the transit ion rate specification, the clock and cke must transit between vih and vil (or between vil and vih) in a monotonic manner. 4. outputs measured for 1.8v at 0.9v with equivalent load: test loads with full dq driver strength. performance will vary with actual system dq bus capa citive loading, termination, and programmed drive strength. 5. a c timing tests have vil and vih with timing referenced to vih/2 = crossover point. if the input transition time is longer than tt (max), then the timing is referenced at vil (ma x) and vih (min) and no long er at the vih/2 crossover point. 6. the clock freque ncy must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) during access or pre-charge states (read, write, including twr, and pre-charge c om mands). cke may be used to reduce the data rate. 7. thz defines the time at which the output achieves the open circuit condition, it is no t a reference to voh or vol. the last valid data element will meet toh before going high-z. 8. the 512m mobile sdram requires 8,192 auto refresh cycles every 64ms (tref). providing a distributed auto refresh command every 7.8125gs meets the refresh require ment and ensures that each row is refreshed. alterna- tively, 8,192 auto refresh commands can be issued in a burst at the minimum cycle rate (trfc), once every 64ms. 9. ac characteristics assume tt = 1ns. 10. auto pre-charge mode only. the pre-charge timing budget (trp) begi ns at x ns for -7 after the first clock delay and after the last write is executed. may not exceed the limit set for pre-charge mode. 11. clk must be toggled a minimum of two times during this period. 12. required clock s are specified by jedec functionality and are not dependent on any timing parameter. 13. ti ming is specified by tcks. clock(s) specified as a reference only at minimum cycle rate. 14. timing is specified by twr plus trp. clock(s) specified as a reference only at minimum cycle rate. 15. timing is specified by twr. 16. based on tck (min), cl = 3. as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 16/48 - rev.1.0 june 2016
timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. burst termination 8.1 termination of a burst write operation 8.2 termination of a burst write operation 9. ac- parameters 9.1 ac parameters for a write timing 9.2 ac parameters for a read timing 10. mode register set 11. power on sequence and auto refresh (cbr) 12. power down mode 13. self refresh (entry and exit) 14. auto refresh (cbr) as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 17/48 - rev.1.0 june 2016
timing diagrams (cont?d) 15. random column read ( page within same bank) 15.1 cas latency = 2 15.2 cas latency = 3 16. random column write ( page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 17. random row read ( interl eaving banks) with precharge 17.1 cas latency = 2 17.2 cas latency = 3 18. random row write ( interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 19. precharge termination of a burst 19.1 cas latency = 2 19.2 cas latency = 3 20. deep power down entry/exit 20.1 deep power down entry 20.2 deep power down exit as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 18/48 - rev.1.0 june 2016
1. bank activate command cycle (cas latency = 3) 2. burst read operation (burst length = 4, cas latency = 2, 3) address clk t0 t t1 t ttt command nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate t rcd : ?h? or ?l? t rc precharge t rrd bank b row addr. command read a nop nop nop nop nop nop nop dout a 0 cas latency = 2 t ck3, i/o?s cas latency = 3 dout a 1 dout a 2 dout a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2, i/o?s dout a 0 dout a 1 dout a 2 dout a 3 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 19/48 - rev.1.0 june 2016
3. read interrupted by a read (burst length = 4, cas latency = 2, 3) 4.1 read to write interval (burst length = 4, cas latency = 3) command read a read b nop nop nop nop nop nop t ck2, i/o?s cas latency = 2 t ck3, i/o?s cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 command nop read a nop nop nop nop write b nop nop dqm dout a 0 din b 0 din b 1 din b 2 must be hi-z before the write command i/o?s minimum delay between the read and write commands = 4+1 = 5 cycles clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t dqz t dqw : ?h? or ?l? as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 20/48 - rev.1.0 june 2016
4.2 minimum read to write interval (burst length = 4, cas latency = 2) 4.3 non-minimum read to write interval (burst length = 4, cas latency = 2, 3) command nop bank a nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command t ck2, i/o?s cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop activate 1 clk interval t dqz t dqw : ?h? or ?l? nop read a nop nop read a nop write b nop nop dqm din b 0 din b 1 din b 2 t ck1, i/o?s cas latency = 2 t ck2, i/o?s cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 c ommand din b 0 din b 1 din b 2 dout a 1 dout a 0 must be hi-z before the write command t dqz t dqw : ?h? or ?l? as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 21/48 - rev.1.0 june 2016
5. burst write operation (burst length = 4, cas latency = 2, 3) 6.1 write interrupted by a write (burst length = 4, cas latency = 2, 3) c ommand nop write a nop nop nop nop nop nop i/o?s din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is ignored after the first data element and the write are registered on the same clock edge. termination of a burst. don?t care command nop write a write b nop nop nop nop nop i/o?s din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 1 clk interval as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 22/48 - rev.1.0 june 2016
6.2 write interrupted by a read (burst length = 4, cas latency = 2, 3) 7. burst write with auto-precharge burst length = 2, cas latency = 2, 3) command nop write a read b nop nop nop nop nop nop t ck2, i/o?s c as latency = 2 din a 0 t ck3, i/o?s c as latency = 3 din a 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 don?t care don?t care don?t care dout b 0 dout b 1 dout b 2 input data must be removed from the i/o?s at least one clock cycle before the read data appears on the outputs to avoid data contention. command clk * t wr * cas latency = 2 cas latency = 3 t ck2, i/o?s t ck2, i/o?s bank activate nop nop nop nop nop nop nop din a 0 din a 1 din a 0 din a 1 t wr t rp t rp begin autoprecharge bank can be reactivated after t rp writea auto-precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 23/48 - rev.1.0 june 2016
7.2 burst read with auto-precharge burst length = 4, cas latency = 2, 3) c ommand read a nop nop nop nop nop nop t ck2, i/o?s c as latency = 2 t ck3, i/o?s c as latency = 3 c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 3 dout a t rp t rp * * * 0 dout a 1 dout a 2 dout a 3 dout a begin autoprecharge bank can be reactivated after t rp 0 dout a 1 dout a 2 nop nop as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 24/48 - rev.1.0 june 2016
8.1 termination of a burst read operation (cas latency = 2, 3) 8.2 termination of a burst write operation (cas latency = 2, 3) command read a nop nop nop burst nop nop nop nop t ck2, i/o?s cas latency = 2 t ck3, i/o?s cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. i/o?s cas latency = 2,3 don?t care as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 25/48 - rev.1.0 june 2016
clk cke cs i/o ras cas we ba dqm 9.1 ac parameters for write timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t17 t18 t19 t20 t15 t23 t21 t22 hi-z ap burst length = 4, cas latency = 2 addr t is t is t ih t ih t is t rcd t rc t rp t is activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a t ih ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck t ch t cl begin auto precharge bank a begin auto precharge bank b t wr t rrd activate command bank b ray cbx cay ray rbx rbx cax rby rby raz raz rax rax t ih as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 26/48 - rev.1.0 june 2016
\ clk cke cs i/o ras cas we ba dqm 9.1 ac parameters for read timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z ap burst length = 2, cas latency = 2 addr t is t ih t ih t is t ih t rrd t rcd t ras t lz activate command bank a activate command bank b activate command bank a precharge command bank a t is t ck2 ax0 ax1 read command bank a read with auto precharge command bank b t rc t rp t ac2 t ac2 t oh t hz t ch t cl bx0 begin auto precharge bank b bx1 t hz cbx ray rbx rbx ray cax rax rax as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 27/48 - rev.1.0 june 2016
10. mode register set clk cke cs ras cas we ba t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 ap addr precharge command all banks mode register set command any command address key 2 clock min. t mrd as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 28/48 - rev.1.0 june 2016
\ 11. power on sequence and auto refresh (cbr) as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 29/48 - rev.1.0 june 2016
12. power down mode burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t is rax rax activate command bank a precharge command bank a power down mode entry power down mode exit any command as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 30/48 - rev.1.0 june 2016
13. self refresh (entry and exit) ba addr ap t clk cke cs i/o ras cas we d qm t2 t3 t4 t0 t1 t t tt t5 t t tt t t t tt tt t t hi-z all banks must be idle self refresh entry begin self refresh exit command t srex self refresh exit command issued self refresh exit t rc is as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 31/48 - rev.1.0 june 2016
14. auto refresh (cbr) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr ax0 ax1 activate command read command precharge command auto refresh command auto refresh command t rfc t rp t rc t ck2 all banks cax rax rax bank a bank a ax2 ax3 (minimum interval) as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 32/48 - rev.1.0 june 2016
15.1 random column read (page within same bank) (1 of 2) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck2 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 33/48 - rev.1.0 june 2016
15.2 random column read (page within same bank) (2 of 2) burst length = 4, cas latency = 3 clk cke cs i/o ras cas we ba d qm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3 as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 34/48 - rev.1.0 june 2016
16.1 random column write (page within same bank) (1 of 2) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck2 activate command bank b cax write command bank b raw raw activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 35/48 - rev.1.0 june 2016
16.2 random column write (page within same bank) (2 of 2) burst length = 4, cas latency = 3 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 36/48 - rev.1.0 june 2016
17.1 random row read (interleaving banks) (1 of 2) clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cby read command bank b read command bank a bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 t ck2 high t rcd t ac2 t rp cax precharge command bank b ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 37/48 - rev.1.0 june 2016
17. 2 random row read (interleaving banks) (2 of 2) burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a 11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 38/48 - rev.1.0 june 2016
18.1 random row write (interleaving banks) (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we a 11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t dpl clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t wr write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t wr as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 39/48 - rev.1.0 june 2016
18.2 random row write (interleaving banks) (2 of 2) burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank b rbx rbx activate command bank a ray ray day3 t dpl cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t dpl t rcd activate command bank a rax rax clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank b rbx rbx activate command bank a ray ray day3 t wr cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t wr t rcd activate command bank a rax rax as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 40/48 - rev.1.0 june 2016
19.1 precharge termination of a burst (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck2 precharge command bank a dax0 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz caz read command bank a az0 az1 az2 precharge command bank a t rp as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 41/48 - rev.1.0 june 2016
19.2 precharge termination of a burst (2 of 2) burst length = 4, 8, cas latency = 3 clk cke cs i/o ras cas we ba d qm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck3 precharge command bank a dax0 precharge termination of a write burst. write data is masked ay0 ay1 ay2 precharge termination precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz of a read burst. as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 42/48 - rev.1.0 june 2016
20.1 deep power down mode entry the deep power down mode has to be maintained for a minimum of 100 s clk cke cs we cas ras addr . dqm dq input dq ou tput high-z t rp precharge comm and deep power dow n entry deep power down mode dp1.vsd normal mo de as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 43/48 - rev.1.0 june 2016
20.2 deep power down exit the deep power down mode is exited by asserting cke high. after the exit, the following sequence is needed to enter a new command: 1. maintain nop input conditions for a minimum of 200 s 2. issue precharge commands for all banks of the device 3. issue eight or more autorefresh commands 4. issue a mode register set command to initialize the mode register 5. issue an extended mode register set command to initialize the extende mode register clk ck e cs ra s ca s we all bank s 200 us au t o deep power do wn aut o t rc mode exi t prec harge refresh refresh register set exte nded mode regis ter set new com mand acce pted her e t rfc t rp as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 44/48 - rev.1.0 june 2016
mobile sdram state diagram self auto idle mrs emrs row precharge write write write read read power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh active active power down precharge power down on a read a read a write a burst stop preall precharge preall deep power down dpds dpdsx as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 45/48 - rev.1.0 june 2016
package diagram 32mx16 54-ball 0.8mm pitch bga as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 46/48 - rev.1.0 june 2016
package diagram 16mx32 90-ball 0.8mm pitch bga as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 47/48 - rev.1.0 june 2016
part numbering system as4c 32m16ms or 16m32mss 6/7 b c / i n dram 32m16=32mx16 16m32=16mx32 ms=mobile sdram 6=166mhz 7=133mhz b = fbga c = commercial ( -25 c ~+85 c) i = industrial (-40 c~+ 8 5 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-6 10 -68 00 fax: 650 -62 0 -9211 www.alliancememory.com copyright ?alliance memory all rights reserved ?copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in l ife -supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. as4c32m16ms-7bcn / AS4C32M16MS-6BIN as4c16m32ms-7bcn / as4c16m32ms-6bin confidential - 48/48 - rev.1.0 june 2016

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